1. Field of the Invention
The present invention relates generally to a nonvolatile semiconductor memory device and a writing method therefor, and more particularly to a nonvolatile semiconductor memory device capable of electrically rewriting information and a writing method therefor.
2. Description of the Prior Art
FIG. 1 is a circuit diagram showing a portion of a memory cell array of a conventional nonvolatile semiconductor memory device, such as an electrically erasable programmable read-only memory (EEPROM), together with voltages for writing and erasing at electrodes, as disclosed in the Digest of Technical Papers, pp. 76-77 of International Solid State Circuits Conference (IEEE), 1987.
Referring to FIG. 1, memory transistors Q1 to Q4 are MOS transistors each provided with a floating gate, and each forming one memory cell. The memory transistors are arrayed in a matrix and the respective source electrodes thereof are connected with a source line SL common to all the cells. A bit line connects the drain electrodes of the memory transistors in the same column. FIG. 1 shows two bit lines BL1 and BL2. A word line connects the control gates of the memory transistors in the same row. FIG. 1 shows two word lines WL1 and WL2. Although FIG. 1 shows four memory transistors Q1-Q4, a memory cell array usually comprises a larger number of memory transistors.
FIG. 2 is a sectional view of a structure of a conventional memory transistor used in the nonvolatile semiconductor memory device shown in FIG. 1. Referring to FIG. 2, a drain region 6 and a source region 7 are formed with a prescribed spacing on a surface of a semiconductor substrate 5. A floating gate 9 is formed on a surface region of the semiconductor substrate 5 near the drain region 6 through a thin oxide film 8 of about 200 .ANG.. The floating gate 9 is in an electrically floating state and part of the gate 9 is located opposite the drain region 6. A control gate 10 of polysilicon is formed on the floating gate 9 through an oxide film. The control gate 10 extends near the source region 7 so that a selector gate is integrally formed. The drain region 6, the control gate 10 and the source region 7 include a drain electrode 11, a control electrode 12 and a source electrode 13, respectively. The bit line BL1 or BL2 shown in FIG. 1 is connected to the drain electrode 11; the word line WL1 or WL2 is connected to the control electrode 12; and the source line SL is connected to the source electrode 13.
Operation of the conventional device shown in FIGS. 1 and 2 will now be described. In this conventional device, "1" is written in all the memory cells in an erase mode and "0" is written only in any memory cell where the data is to be written in a write mode.
First, erasing operation will be described. When all the bit lines BL1, BL2 etc. are supplied with a high voltage Vpp with all the word lines WL1, WL2 etc. being at zero volt, a high field is generated between the floating gate 9 and the drain region 6 shown in FIG. 2. Thus, electrons stored in the floating gate 9 are drawn into the drain region 6 through the thin oxide film 8 by electron tunneling. At this time, the floating gate 9 is depleted of electrons and accordingly a threshold voltage of the memory transistor viewed from the control gate 10 is lowered compared with that before the erasing operation. This state is referred to as an erase state and a logic "1" is assigned to that state.
As to writing operation, the case of writing in the memory transistor Q3 will be particularly described. Writing procedures are the same as those in a program in an EPROM (Electrically Programmable ROM). Voltages are applied in the following manner. The selected bit line BL2 is at Vpp; the non-selected bit line BL1 is at zero volt; the selected word line WL1 is at Vpp; the non-selected word line WL2 is at zero volt; and the common source line SL is at zero volt. Consequently, hot electrons are generated in the vicinity of the drain region 6 of the memory transistor Q3 and those hot electrons are accelerated by the high voltage Vpp applied to the control gate 10 so as to be introduced into the floating gate 9. As a result, electrons are stored in the floating gate 9 and the threshold voltage of the memory transistor viewed from the control gate 10 becomes higher than that prior to the writing operation. Thus, a write state is established and a logic "0" is set.
In the above described conventional device, it is not necessary to erase stored information by using ultraviolet rays, because like an EPROM stored information can be electrically erased with the device being mounted on a board. In addition, a memory cell of the above described conventional device can be formed by a single transistor, not by two transistors as in an EEPROM, and thus chip area can be reduced.
However, if writing operation is to be performed as described above in the conventional nonvolatile semiconductor memory device by injection of hot electrons, it is necessary to provide a power supply having a large current driving capacity. If a high voltage developed by an internal power supply of the device is utilized, the current driving capacity is small and writing operation cannot be performed in a satisfactory manner. Accordingly, the conventional device requires an external power supply having a large current driving capacity. Thus, an external power supply is provided in the conventional device for satisfactorily performing operation in addition to an internal power supply, which causes the circuit connected with the device to be large in size, resulting in considerable increase of the manufacturing cost. In addition, writing operation by injection of hot electrons produces an excessively large quantity of electrons in the thin oxide film 8, causing deterioration of the thin oxide film 8. As a result, the number of erasing and writing operations effectively performed is considerably decreased (to about 10.sup.3).
FIG. 3 is a diagram for explaining a writing method of an integrally formed type nonvolatile memory cell matrix disclosed in Japanese Patent Laying-Open Gazette No. 99997/1986. According to this gazette, in the write mode, a high voltage Vpp is applied to the bit line BL2 related to the selected memory transistor Q3 with the other bit lines being at zero volt and zero volt is applied to the word line WL1 related to the selected memory transistor Q3 with an intermediate voltage 1/2.Vpp being applied to the other word lines. In the above described writing method, a high field is generated between the floating gate and the drain region of the selected transistor Q3, making it possible to write information by electron tunneling. Thus, the above described writing method appears to be able to eliminate the above described disadvantages of the conventional device shown in FIG. 1. However, in the writing method in FIG. 3, both of the memory transistors Q2 and Q4 are turned on and current leakage paths as shown by the arrows in FIG. 3 are formed. As a result, large current flows from the power supply generating the high voltage Vpp to be applied to the bit line BL2, to ground. Consequently, a power supply having a large current driving capacity needs to be used as the power supply for generating the high voltage Vpp, and an internal power supply accordingly cannot be used. Therefore, the writing method shown in FIG. 3 also requires an external power supply, which involves the disadvantage that the circuit is large in size and expensive.